Chip Estimate

ARLINGTON, Va., USA – JULY 13, 2026 – JEDEC Solid State Technology Association, the global leader in standards development for the microelectronics industry, today announced the publication of JESD330-4: Standard Package High Bandwidth Memory (SPHBM4). SPHBM4 uses the same DRAM dies as HBM4, commonly used in artificial intelligence accelerators, with a new interface base die that enables mounting on standard organic substrates rather than silicon substrates.

Keysight and Rambus collaborated to demonstrate that side-channel vulnerabilities in an Advanced Encryption Standard (AES) design can be detected at the pre-silicon stage. Rambus selected a pre-release version of one of its AES designs, in which an SCA vulnerability had previously been identified through traditional Field-Programmable Gate Array-based (FPGA) validation testing.

Collaboration combines Intel's advanced packaging expertise with Lens Technology's precision glass processing capabilities to deliver enhanced performance for future AI and datacenter workloads SANTA CLARA, Calif. & CHANGSHA, China - Intel Corporation and Lens Technology today announced a strategic collaboration focused on enabling new technologies for advanced semiconductor packaging.

News Summary: NVIDIA expands NVIDIA Agent Toolkit with re-architected NVIDIA PhysicsNeMo libraries and updated NVIDIA CUDA-X libraries, enabling software developers to build autonomous AI engineers with AI physics skills, accelerated solvers and quantum chemistry capabilities. NVIDIA Nemotron 3 Ultra leads among open models in agentic register-transfer level coding with the ACE-RTL agent from NVIDIA Research, helping enterprises build customizable AI agents for chip design and verification.

DAC 2026 Wrap-Up: AI-Powered Engineering Moves from Vision to Workflow Reality Explore Cadence IP Every year, Design Automation Conference (DAC) brings big announcements, packed demos, and deep technical conversations—and this year at DAC 2026, the inflection point was AI moving from point-task assistance to workflow-level autonomy.

10th Aug 2026. – Applications such as artificial intelligence (AI), high-performance computing (HPC), networking, automotive electronics, and data-centre processors increasingly require high-bandwidth, low-latency communication between multiple dies while maintaining power efficiency and simplifying system integration.

Explore Synopsys IP here Introduction As multi-die designs continue to scale across AI and high-performance computing (HPC), the demand for higher bandwidth, tighter integration, and predictable system-level performance has never been greater. Designs are integrating more dies (also called chiplets) within a single package, driving the need for faster, more robust die-to-die connectivity.

CAMPBELL, Calif., – August 6, 2026 – Arteris, Inc. (Nasdaq: AIP), a leading provider of semiconductor technology for accelerating innovation in the AI era, today announced the appointment of Saurabh Sinha as Chief Financial Officer, effective September 8, 2026. Mr. Sinha succeeds Nick Hawkins, who is retiring after seven years with the company. Mr. Hawkins will provide continued support in an advisory role to facilitate a seamless transition.

ATS296X-series combines Actions’ latest wireless audio technology with Ceva's Bluetooth® High Data Throughput platform, extending a collaboration that has delivered more than 100 million wireless audio SoCs ROCKVILLE, MD., and ZHUHAI, China - August 4, 2026 – Ceva, Inc. (NASDAQ: CEVA), the leading licensor of silicon and software IP for the Smart Edge, and Actions Technology Co., Ltd.

July 30, 2026 - TOKYO, Japan — Renesas Electronics Corporation (TSE: 6723), a premier supplier of advanced semiconductor solutions, today announced its third-generation (Gen 3) DDR5 Multiplexed Rank Dual In-Line Memory Module (MRDIMM) chipset solutions, delivering DDR5 server-class MRDIMM speeds up to 16,000 mega transfers per second (MT/s).