Chip Estimate

BUDAPEST, Hungary – September 23, 2026 – aiMotive today announced a joint technology demonstration of explicit, per-layer neural network workload placement across aiMotive’s aiWare5 automotive NPU IP (Neural Processing Unit Intellectual Property) and the Cadence Tensilica NeuroEdge 130 AI Co-Processor. Conducted in pre-silicon simulation, the demonstration illustrates how SoC architects can define and adjust processing boundaries across independently developed AI engines and toolchains.

Scalable 32-bit and 64-bit RISC-V compute spanning embedded control, functional safety and vector/matrix AI acceleration—backed by a complete software and development ecosystem. T2M announces the expansion of its RISC-V CPU IP cores portfolio, enabling chip companies to scale from embedded and real-time control to application-class processing and AI acceleration within a flexible RISC-V architecture.

Companies form strategic partnership to dramatically advance and accelerate semiconductor innovation News Highlights: Companies sign multi-year agreement to collaborate as preferred partners to develop and deliver GPT-Synopsys, a specialized model for chip design that brings together OpenAI's frontier AI with Synopsys' trusted EDA tools and chip design expertise OpenAI to license Synopsys' trusted electronic design automation (EDA) tools for development of the specialized model Synopsys &...

News Highlights: Strategic engagement to accelerate the engineering of Amazon custom chips and AWS infrastructure using Synopsys' silicon IP and AI-powered engineering software solutions Multi-year, $1B+ agreement marks the expansion of Synopsys' silicon IP business to serve increasing demand for application-optimized IP while evolving to a license-plus-royalty business model that aims to deliver value to both companies as production volumes grow Synopsys to accelerate product development...

Explore Rambus IP here Securing the Modern Data Center Data centers have become the foundation of the digital economy. Cloud services, AI training and inference, high-performance computing, and increasingly data-intensive enterprise applications all depend on infrastructure that can process and move vast amounts of information at scale.

Keynote will explore scaling silicon-level functional safety and hardware dependability for increasingly complex autonomous vehicle systems GAINESVILLE, Fla. — September 29, 2026 — The 2027 Design and Verification Conference and Exhibition (DVCon U.S.), sponsored by Accellera Systems Initiative, today announced Jyotika Athavale, a leader in silicon functional safety at Waymo, as its invited keynote speaker.

Please log in to watch video A holistic and optimized approach to embedded cybersecurity at IP Soc Days Korea 26 Secure-IC | 21:34 Artificial Intelligence and Post-Quantum Cryptography are reshaping the cybersecurity landscape for embedded systems. As devices become more intelligent, connected, and long-lived, organizations must rethink how security is designed and managed across the entire product lifecycle.

Please log in to watch video SystemChat Episode 1: Let’s Chat about Memory Cadence | 21:08 Embedded Computing Design editor in chief, Ken Briodagh, interviews Frank Ferro, Group Director, IP Product Management at Cadence, for a discussion on system of Memory and Storage in the inaugural podcast episode of SystemChat.

Please log in to watch video Cadence-Intel UCIe Interoperability Demo at Chiplet Summit 2026 Cadence | 1:36 Intel Product Line Manager and co-chair of UCIe Marketing Working Group, Stephen Wong, demonstrated joint Cadence-Intel UCIe interoperability. Watch the Intel-Cadence demo of their respective UCIe IPs interoperating in silicon achieving successful data transfer with wide open eyes. The demo was showcased during Chiplet Summit 2026.

Hsinchu, Taiwan — M31 Technology (M31), a global silicon intellectual property (IP) provider, today unveiled a technology collaboration with Rambus Inc. for its MIPI CSI (Camera Serial Interface) Controller and MIPI DSI (Display Serial Interface) Controller technologies.