More Than Moore

In April 2024 I pulled on a bunny suit at Intel’s D1X fab in Hillsboro, Oregon, and stood a few feet from a machine the size of a bus and worth a small nation state. Intel Fellow Mark Phillips explained this was ASML’s first High-NA EUV scanner, 165 tons of it. Installation had just wrapped and calibration had begun, but realistically still another few months before test wafers could be run.

Memory is one of the foundational technologies behind every major compute transition, and right now it is more visible than it has been in years. As AI infrastructure expands across training, inference, and large scale cloud deployments, demand for high performance DRAM and storage has moved sharply up the industry agenda.

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Both Samsung and SK Hynix have working LPDDR6 silicon. Just seven months after the JEDEC specification was ratified. The effective bandwidth at 14.4 Gbps is 38.4 GB/s per die. SK Hynix chased bandwidth, Samsung chased efficiency. The shmoo plots tell the story on where the silicon is right now. This is just the first generation of LPDDR6 silicon.

When people talk about semiconductors, most of the attention goes to the visible parts of the system: the CPU, the GPU, the XPU, the DRAM, the HBM, or the networking silicon. Much less attention goes to the components that make all of that hardware run together, whether that’s to do with things like power or in this case, clocks and timing. The thing is, every modern electronic system needs timing.

Five things you need to know before reading: This is not a GPU, and it is not trying to be. Spyre is a 75 W single-slot PCIe inference card, designed to fit in IBM Z and Power systems. Spyre is already shipping in systems. This overview is a summary of a detailed technical disclosure at ISSCC 2026. The 8-year development timeline is real and deliberate. IBM ran five generations of silicon across three process nodes before releasing the production chip.

Cadence has spent the last several years trying to broaden what EDA means, pushing further up the stack into system design, digital twins, robotics, and now agentic AI. But while much of the wider AI market is still debating copilots, wrappers, and workflow automation, the more interesting question for engineering software is whether these models can actually become part of the design environment itself.

When people talk about the semiconductor industry, most of the attention goes to the visible parts: the chips, the process nodes, the packaging technologies, the benchmark slides, and the race for more performance per watt. Far less attention lands on the software and infrastructure that makes those chips possible in the first place. But as chip design has become more complex and we drive to more advanced process nodes, the design becomes tightly coupled to manufacturing.

There are only a handful of people in the semiconductor industry who can genuinely claim to have lived through nearly every major shift in modern compute from the inside. Pat Gelsinger is one of them. His career stretches back through Intel’s formative decades, an era when CPU performance scaling still defined the direction of the industry, through the build-out of enterprise infrastructure and virtualization.

Update 4/4 12:15pm UK: Dylan posted the following on social media addressing the issue. I want to speak directly about a situation involving a former employee and recent legal filings. This is not something we take lightly. In January 2026, SemiAnalysis terminated an employee due to severe misconduct.