Semiconductor Engineering
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Semiconductor Engineering was created by chip architects, engineers, journalists, end users, industry organizations and standards bodies to provide deep insights into the increasingly complex task of designing, testing, verifying, integrating and manufacturing semiconductors, as well as insights into the market dynamics that make it all possible.
The goal of this site is to provide useful, independently developed content through targeted monthly newsletters, weekly updates, timely news alerts, videos, independent research, and a portal that serves as a forum for exchanging ideas and answering questions. While this site is supported by sponsors, all content developed by our writers adheres to the highest journalistic standards for editorial integrity and unbiased reporting. All stories are professionally written and edited by independent journalists and engineers with deep industry knowledge and experience, and all vendor involvement is limited to providing expertise rather than promoting their products.
Sperling Media Group LLC was formed in 2008 to provide a free flow of unbiased information about technology and business issues in narrow but technologically challenging markets. At a time when complexity is at its peak and real insight is essential, the number of independent sources for that information is shrinking. Source
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| Scope | International |
|---|---|
| Language | English |
| Country | United States of America |
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Recent Articles
Search ArticlesSimulations Pinpoint Leakage Pathway In GAAFETs (Sandia, Luxembourg)
Researchers at Sandia National Laboratories and Luxembourg Institute of Science and Technology published a technical paper titled “Revealing New Leakage Paths in GAAFETs using Predictive First-Principles Simulations.” Abstract Excerpt: “Gate-All-Around Field-Effect Transistors (GAAFETs) are emerging as successors to Fin Field-Effect Transistors (FinFETs) and are central to continued scaling at advanced semiconductor nodes.
Characterization of HBM Power Consumption (ETH Zurich, NYU)
Researchers at ETH Zürich and New York University published a technical paper titled “Understanding the Power Consumption of Modern High Bandwidth Memory: Experimental Analysis and Modeling Using Real HBM2 DRAM Chips.” Abstract Excerpt: “We perform the first comprehensive experimental characterization of power consumed by real HBM2 DRAM chips.
Accelerating Advanced IC Package Design: A Methodology for Early and Iterative Optimization of Chiplet Integration
Today’s multi-chip and chiplet solutions are leading the way for the “More than Moore” vision, with companies leveraging packaging technologies to create value and differentiate themselves from their competitors. Through-silicon via (TSV), wafer-level packaging (WLP), and 3D stacking technologies offer a wide range of packaging options for all form factors. Figure 1 illustrates a common example of 3D die/wafer stacking vs the traditional 2D system-on-a-chip (SoC). Fig.
Generative AI On A General-Purpose Neural Processor (GPNPU)
Generative-AI workloads evolve on a quarterly cadence, with novel attention variants, quantization formats, and routing schemes appearing faster than fixed-function neural-processor silicon can be respun.
How To Define CPU And Software Stack Performance For Agentic AI
Agentic AI changes the CPU performance problem. A completed task can involve repeated model calls, retrieval, state management, tool execution, application interactions, policy checks and validation loops. Accelerators remain central to model execution, while CPUs coordinate and execute much of the surrounding system path from user intent to completed work. This paper proposes a use-case-driven framework for evaluating that CPU contribution.
Why Heat Is Becoming A Bigger Chip Design Issue
Key Takeaways: Complex designs now require voltage, timing, resistance, power, and temperature to be analyzed together, and in the context of each other. Vertical scaling will require new materials and cooling options. Agentic AI could help engineers cross traditional discipline silos, which will be necessary because thermal is a system-level problem.
Blog Review: Oct. 14
Synopsys’ Thomas Andersen finds that as more execution moves into autonomous workflows, the engineer’s focus is shifting toward defining objectives, guiding decisions, evaluating tradeoffs, and determining whether an outcome is ready to move forward. Siemens’ Sriram Bhaskar Teja Mundru shows how UALink over UCIe 3.0 improves cross-vendor interoperability and enables the development of scalable AI systems by standardizing interfaces, form factors, and flow control mechanisms.
Simplify Electronic-Photonic Design Workflows: eBook
Combining light-based components with traditional electronics is not straightforward. Conventional electronic design automation (EDA) workflows were never built to handle the complex physics and deep integration demanded by photonics. As optical and electronic technologies converge, engineers face tighter cross-domain coupling and unprecedented system-level complexity. Addressing these challenges requires a new design paradigm: electronic photonic design automation (EPDA).
Agentic AI Automates RTL Waveform Analysis And Debugging (Columbia, Google)
Researchers at Columbia University, Google DeepMind, and Google published a technical paper titled “Back to the Future: Rethinking EDA Infrastructure for Agentic Systems in Chip Design Verification.” Abstract “The unprecedented computational scale of modern artificial intelligence depends on complex, multi-billion-transistor Systems-on-Chip, yet the workflows that verify these chips remain stubbornly manual.
Chip Industry Technical Paper Roundup: Oct. 13
AI workloads are pushing automotive sensors harder, forcing engineers to rethink how long safety-critical systems can be trusted. How to achieve a 10X productivity improvement using AI agents. Plenty of cash for AI and its enablers; 80 startups raise over $6B. S. Korea goes All In on AI; new Dresden power fab; Intel expansion; GM secures memory supply; AI power management funding; mature-node foundry capacity; 300mm fab equipment; McKinsey's map of strategic IC supply; security threats; AI burnout.