Semiconductor Engineering
VerifiedOnline/Digital
Semiconductor Engineering was created by chip architects, engineers, journalists, end users, industry organizations and standards bodies to provide deep insights into the increasingly complex task of designing, testing, verifying, integrating and manufacturing semiconductors, as well as insights into the market dynamics that make it all possible.
The goal of this site is to provide useful, independently developed content through targeted monthly newsletters, weekly updates, timely news alerts, videos, independent research, and a portal that serves as a forum for exchanging ideas and answering questions. While this site is supported by sponsors, all content developed by our writers adheres to the highest journalistic standards for editorial integrity and unbiased reporting. All stories are professionally written and edited by independent journalists and engineers with deep industry knowledge and experience, and all vendor involvement is limited to providing expertise rather than promoting their products.
Sperling Media Group LLC was formed in 2008 to provide a free flow of unbiased information about technology and business issues in narrow but technologically challenging markets. At a time when complexity is at its peak and real insight is essential, the number of independent sources for that information is shrinking. Source
Actions
Media Outlet details
| Scope | International |
|---|---|
| Language | English |
| Country | United States of America |
Similarweb UVM
|
Request pricing |
Comscore UVM
|
Request pricing |
Recent Articles
Search ArticlesM3D 6T SRAM With BEOL Pass-Gates at 2nm (Georgia Tech, Synopsys)
Researchers from Georgia Institute of Technology and Synopsys published a technical paper titled “A Process-Aware Hybrid Si/IGO Monolithic-3D 6T SRAM with BEOL Pass-Gates for the 2nm Node.” Abstract Excerpt: The paper proposes “a monolithic-3D (M3D) 6T SRAM at the 2nm node” that integrates BEOL IGO pass-gates with an all-silicon nanosheet latch, buried power rails, and Ru interconnects.
Intrinsic Polarization Superjunctions Boost GaN-On-Silicon Power Devices (EPFL)
Home > Home > Intrinsic Polarization Superjunctions Boost GaN-On-Silicon Power Devices (EPFL) Researchers from École Polytechnique Fédérale de Lausanne (EPFL) published a technical paper titled “Intrinsic polarization superjunctions in III-nitride heterostructures for efficient power electronics.” Abstract Excerpt: “III-nitride semiconductors combine a wide bandgap with low sheet resistance and, thus, can be used for efficient power electronics.
Molecular Dynamics Study Explains Aluminum Dopant Activation In 4H-SiC (TU Wien, Silvaco)
Home > Home > Molecular Dynamics Study Explains Aluminum Dopant Activation In 4H-SiC (TU Wi...
Hybrid HBM-HBF Architecture in LLM Inference (University of Oxford)
Researchers at the University of Oxford published a technical paper titled “Hardware-Managed Heterogeneous High-Bandwidth Memory and Flash in LLM Inference Systems.” Abstract Excerpt: “ High-Bandwidth Flash (HBF) offers a denser alternative, providing 16x more capacity per stack at comparable bandwidth.
Cycle-Level Simulator for Distributed GPUs For AI Workloads (Purdue)
Researchers from Purdue University published a technical paper titled “Architecting the Next Generation of Asynchronous, Distributed GPUs for the AI Era.” Abstract Excerpt: The paper presents a “cycle-level simulation framework” for modern GPU generations including Ampere, Hopper, and Blackwell. It also reports validation against physical silicon, including a “99% Pearson correlation coefficient” on H100 GPU results. Find the technical paper here. August 2026.
Programmable Silicon Photonics Filter Enables Continuous Laser Wavelength Tuning (UiT, Stanford)
Researchers at UiT The Arctic University of Norway and Stanford University published a technical paper titled “Intracavity Laser Wavelength Tuning by a Programmable Forward-Only Silicon Photonics Interferometer Mesh.” Abstract Excerpt: “We exploit a recently proposed concept for a programmable, mechanically robust, and tunable nonresonant silicon photonic integrated circuit filter and experimentally demonstrate it for tuning an erbium-doped fiber laser ring cavity.
Predicting Post-Route PPA from Macro and Standard-Cell Placements (U. of Alberta)
Researchers from University of Alberta published a technical paper titled “PPAPlace: Differentiable Cross-Stage Objectives for Chip Placement Optimization.” Abstract: “Macro placement significantly affects a chip’s post-route performance, power, and area (PPA). Most placement methods optimize half-perimeter wirelength (HPWL) as the primary objective.
Rowhammer Backdoor Injection Attack During Inference (Northeastern)
Researchers from Northeastern University published a technical paper titled “ROBBIN: Rowhammer-Based Backdoor Injection during Inference.” Abstract excerpt: “This work presents ROBBIN, a hardware-aware Rowhammer-based backdoor injection attack that integrates the device-specific vulnerability into the backdoor construction process.
Open-Source Benchmark Suite For 2.5D/3D Heterogeneous Integration Research in Physical Design (UCLA)
Researchers from University of California, Los Angeles published a technical paper titled “An Open-Source Benchmark Suite of 3D-IC Testcases.” Abstract Excerpt: The paper presents an “open-source suite of 3D-IC benchmark testcases” and provides “reusable virtual chiplet models covering compute, memory, I/O, analog, and substrate components.” Find the technical paper here. August 2026. Soni, Rohan, Jooyeon Jeong, Alexander Graening, Anthony Foo, Richard Chen, and Puneet Gupta.
Ferroelectric Tuning Reduces Optical-Interconnect Stalls In LLM Training (Georgia Tech)
Home > Home > Ferroelectric Tuning Reduces Optical-Interconnect Stalls In LLM Training (Geo...