Semiconductor Engineering
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Semiconductor Engineering was created by chip architects, engineers, journalists, end users, industry organizations and standards bodies to provide deep insights into the increasingly complex task of designing, testing, verifying, integrating and manufacturing semiconductors, as well as insights into the market dynamics that make it all possible.
The goal of this site is to provide useful, independently developed content through targeted monthly newsletters, weekly updates, timely news alerts, videos, independent research, and a portal that serves as a forum for exchanging ideas and answering questions. While this site is supported by sponsors, all content developed by our writers adheres to the highest journalistic standards for editorial integrity and unbiased reporting. All stories are professionally written and edited by independent journalists and engineers with deep industry knowledge and experience, and all vendor involvement is limited to providing expertise rather than promoting their products.
Sperling Media Group LLC was formed in 2008 to provide a free flow of unbiased information about technology and business issues in narrow but technologically challenging markets. At a time when complexity is at its peak and real insight is essential, the number of independent sources for that information is shrinking. Source
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| Scope | International |
|---|---|
| Language | English |
| Country | United States of America |
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Recent Articles
Search ArticlesBlog Review: July 15
Cadence’s Anupriya K explains how Address Translation Services (ATS) acts as the fast lane for PCIe memory access by caching address translations directly on the device and what makes it one of the toughest verification problems to solve. Synopsys’ Greg Sorber considers the economic potential of physical AI and the impact that embedding intelligence into robots, vehicles, and equipment will have on future factories, hospitals, and city streets.
AI In Chip Design: Lots Of Promise, Plenty Of Unanswered Questions
Key Takeaways: AI opens the door to exploring a much larger solution space, similar to what high-level synthesis did years ago, but questions persist about the impact of increasing reliance what is essentially a black-box chip design. There is no consistent answer to how successful AI will be, where it will succeed or fail, or how it will apply to different markets and EDA customers.
AI Models On The Edge
Home > Low Power-High Performance > AI Models On The Edge Customizing NPUs without sacrificing flexibility. Moving from large language models in the cloud to small language models at the edge is much more complicated than just slimming down the algorithms. It requires changes in both hardware and software, and the constraints can vary greatly from one market segment to another.
Research Bits: July 14
Cerebellum-inspired memtransistor Researchers from Northwestern University and University of Illinois at Chicago developed a cerebellum-inspired memtransistor for anomaly detection that ignores expected inputs and rapidly detects unexpected events while using less energy than conventional AI.
EDA Revenue Up 12.7%; APAC Roars Back
Worldwide EDA and semiconductor IP revenue reached $5.748 billion in Q1 2026, a 12.7% increase compared to the same period in 2025. The key driver continues to be demand for tools used to create AI server chips, with computer-aided engineering up 15.5% to $2.018 billion. There was a noticeable bump in Chinese sales due to a relaxation of export restrictions, rising $31% to $508 million, versus $388 million in Q1 2025.
Near-memory Dequantization Architecture In Custom HBM for LLM inference (SK hynix)
Researchers from SK hynix published a technical paper titled “StreamDQ: Near-Memory Weight DeQuantization in Custom HBM for Scalable AI Inference Acceleration.” The paper proposes StreamDQ for “a lightweight architectural enhancement that enables on-the-fly dequantization in the memory subsystem for high-throughput, large-batch LLM inference,” and reports “up to 7.08× speedup and 90.23% lower energy” for mixed-precision GEMM. Find the technical paper here. July 2026.
Startup Funding: Q2 2026
Investors kept pouring money into AI hardware startups in the second quarter of 2026. While companies focused on chips for AI data centers have largely dominated the funding over the past year, startups creating edge silicon re-emerged this quarter as investors see the appeal of physical AI and real-time on-device applications.
Change Is Tough
When I was actively involved in the creation of standards for the EDA and semiconductor industry, it was often joked that the great thing about standards is that there are plenty to choose from. According to the Internet, this quote can either be attributed to Grace Murray Hopper (an incredible pioneer in the development of modern programming languages and a rear admiral in the Navy), or Andrew S.
Rethinking Ethernet For The AI Scale-Up Era: Inside ESUN
Every generation of AI infrastructure has redefined what “the network” means. In today’s training clusters — scaling from hundreds to hundreds of thousands of accelerators — the interconnect is no longer a supporting actor. It has become a first-order determinant of system throughput, utilization, and cost per token. Accelerators inside these systems don’t just move data; they synchronize on it, step after step. When even a small fraction of that traffic is late, expensive compute sits idle waiting.
Innovation First, AI Second: Lessons From SSN And The Future Of Test
By Marc Hutner and Ron Press Artificial Intelligence is rapidly becoming pervasive in society and across semiconductor development processes. We have to be careful not to apply AI to solve optimizations and challenges of existing methods but pair with engineering innovation for evolutionary results. One example is the application of scan test data in multi-core designs. AI can optimize the device IO bandwidth allocation to each core based on the core pattern size.