Tech Design Forum Blog

By TDF Staff |  No Comments  |  Posted: June 6, 2024 Topics/Categories: Blog - EDA  |  Tags: design for security, hacking, static analysis | Organizations: RealIntent Real Intent has developed a tool for identifying potential security issues in chip designs at the sign-off stage. Sentry Hardware Security analyzes datapaths within the hardware, ensuring those identified as sensitive adhere to security protocols.

By TDF Staff |  No Comments  |  Posted: June 6, 2024 Topics/Categories: Blog - IP  |  Tags: 3DIC, AI, Arm Cortex-A, chiplet, HBM | Organizations: Alphawave, Arm Alphawave Semi has collaborated with Arm on the development of an advanced compute chiplet based on Arm’s Neoverse compute subsystems.

By TDF Staff |  No Comments  |  Posted: May 29, 2024 Topics/Categories: Blog - EDA  |  Tags: IEDM, machine learning, post-CMOS devices, RF | Organizations: IEEE The 70th annual IEEE International Electron Devices Meeting (IEDM) is putting together its next conference under the theme under the theme “shaping tomorrow’s semiconductor technology”.

By Chris Edwards |  No Comments  |  Posted: May 29, 2024 Topics/Categories: Blog - IP  |  Tags: 3DIC, bonded wafers, silicon photonics, wafer bonding | Organizations: IMEC Imec is presenting at this weel’s IEEE Electronic Components and Technology Conference (ECTC) a die-to-wafer bonding process that can reduce the bond-pad pitch to 2µm with an overlay error of less than 350nm.

By Chris Edwards |  No Comments  |  Posted: May 13, 2024 Topics/Categories: Blog - EDA, Embedded  |  Tags: 3DIC, advanced packaging, AI, HPC, IoT, sensor hub | Organizations: IBM, IEEE, Intel Foundry Services, KAIST This year’s Electronic Components and Technology Conference (ECTC), held in Denver at the end of May, will continue its focus on the role of packaging in keeping silicon scaling on track.

By Chris Edwards | No Comments | Posted: May 2, 2024 Topics/Categories: Blog - EDA, IP | Tags: 3nm, backside power delivery, finFET, monolithic 3DIC, power analysis | Organizations: IMEC, Intel, Samsung Electronics Intel will describe its 3nm-node finFET process at the VLSI Symposium on Technology and Circuits in Hawaii in mid-June alongside papers from a variety of semiconductor organisations that investigate the viability of backside contacts and power distribution, and novel memory...

By Paul Dempsey |  No Comments  |  Posted: April 29, 2024 Topics/Categories: Blog Topics, Blog - PCB  |  Tags: design flow, design management, HPC, mil/aero, single board computer, virtual design | Organizations: Abaco Systems, AMETEK, Siemens EDA One of the main challenges posed during the Covid-19 pandemic was that of bringing together complex projects at a time when communications were necessarily limited.

By Paul Dempsey |  No Comments  |  Posted: April 29, 2024 Topics/Categories: Blog - PCB  |  Tags: design management, design strategy, ebook, PCB routing | Organizations: Siemens EDA Perhaps the question of manual vs automated PCB routing was settled some time ago. But, now more than ever, factors such as rising quality demands, complexity and risks inherent in project delay make the case for automation.

PCB routing is best served by a mixture of manual and automated tasks. A new e-book describes the boundaries between the two.

Learn which routing techniques offer a PCB designer the best balance between automation and control by applying them in harmony.