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Arm has squeezed more performance from its Lumex Ultra CPU, but the company’s new GPU advances its mobile platform the furthest. At the same time, Arm has introduced the Neoverse N4 for servers and high-end embedded chips. Because Arm’s smartphone-chip licensees update their flagship processors annually, Arm revises its designs (IP) at the same pace.

At Hot Chips 2026, companies unveiled new processors and discussed related topics, such as memory and networking. Large companies dominated the agenda, and several had multiple speaking slots. Below are observations from the conference, covering the majority of the program.

Join Byrne-Wheeler Report hosts Joe and Bob as they discuss key disclosures from Hot Chips 2026, including Intel’s Diamond Rapids Xeon, AMD’s Helios MI450 platform, NVIDIA’s LPX/LPU architecture, Cerebras’s CS-4 wafer-scale engine, and OpenAI’s Jalapeño ASIC. If you work in AI hardware, semiconductors, GPUs, CPUs, interconnects, or data center architecture, this episode delivers insight unavailable in press releases and vendor pitches.

AMD has acquired Taalas, an AI-acceleration startup that hardwires models to achieve eight times the token rate of its nearest competitor while requiring a fraction of the power. Located in Toronto and founded by Tenstorrent cofounder Ljubisa Bajic, Taalas has demonstrated a chip implementing the Llama 3.1 8B model. AMD states that the company will integrate the startup’s technology in systems with Instinct GPUs. For the AI market, AMD has competitive GPUs such as the MI455X.

AMD has aligned its data-center GPU architecture with that of market leader Nvidia. However, AMD highlights the token-throughput and efficiency gains of the new MI455X over the previous-generation MI355X instead of touting how customers will find it easier to port their AI models to the GPU. Implementing the CDNA 5 architecture, the MI455X is the heart of the Helios-400 platform and will ship to customers later this quarter.

In Episode 16 of the Byrne-Wheeler Report, Joe and Bob discuss the latest developments in AI hardware, including disclosures at AMD’s Advancing AI day, NVIDIA Vera, and upcoming conferences Hot Chips and OCP APAC. They analyze new processor architectures, interconnect standards, and market implications for AI and data center computing. Click above to play the Byrne-Wheeler Report on YouTube or search for it on your favorite podcast platform.

NextSilicon, a startup focusing on processors for high-performance computing, is developing a server-class 64-core CPU chip called Arbel. A RISC-V design based on a core NextSilicon employed in its Maverick-2 data-flow compute accelerator, Arbel is due to ship in early 2028. A development chip is already in customers’ hands. The RISC-V architecture has been mooted as an alternative to Arm Android-based smartphones, automotive electronics, and hyperscalers’ servers.

AMD has revealed the first models of its sixth-generation Epyc product line, Venice. Based on the new Zen 6 and Zen 6c cores, the now-shipping processors offer two packaging options. Maximum core count increases from 192 in the previous Turin generation to 256. As before, the highest-frequency chips boost to 5 GHz. Across the board, peak memory throughput is more than double that of Turin.

Nvidia is mounting a charm offensive for its Vera microprocessor, touting its sizable strengths in key areas and retconning it into a framework of how data-center processors have changed. If this framework is valid, the company is at least one generation ahead of other server-processor suppliers. At the same time, Nvidia claims that competing products (implicitly, yet specifically, AMD Epyc) have structural shortcomings that limit their performance in the changed market.

Demand for faster AI processing of ever larger models is forcing memory-technology improvements. One of the simplest digital circuits, memory can boost processor performance. The bigger and faster it is, the more memory can reduce the time compute units spend waiting for data stored far away. Improvements to memory have been incremental.