Skip To Main Content
int Status on Muck Rack

int Status

As seen in: CSDN
Is this you? As a journalist, you can create a free Muck Rack account to customize your profile, list your contact preferences, and upload a portfolio of your best work. Claim your profile
Back to int Status’s profile

Articles by int Status

Precision Analog Measurement

|
By Adam Taylor, int Status
Things used in this project × 1 × 1 × 1 × 1 × 1 Introduction One of my proudest engineering achievements was being involved with the ESA Plato mission. We designed the electronics and FPGAs that control the thermal base for the camera system. As you can imagine, such a system needs incredible stability and accuracy in its temperature measurements.
Open in Who Shared Issue with article?

Illuminating Vivado ChipScope ILAs (UltraScale+)

|
By Adam Taylor, float scaleFactor, int Status
Things used in this project × 1 × 1 Introduction One of the most interesting industry statistics is that 84% of FPGA designs make it into the field with at least one bug. Of course, we can try to minimize this by following a good FPGA development process which enables a structured approach. Such an approach enables a high-quality design to be completed.
Open in Who Shared Issue with article?

Using ChipScope to Debug AMD Versal Designs

|
By Adam Taylor, int Status
Things used in this project Alinx VD100 Versal Edge AI SoM × 1 × 1 Alinx AN7000 7-inch screen module RGB 24 bit color 1280 *720 × 1 Introduction The Versal AI Edge series offers a powerful range of System-on-Chip (SoC) devices specifically optimized for edge applications—particularly those involving AI and machine learning.
Open in Who Shared Issue with article?

PYNQ-Z2 HDMI Usage - 4: Video Processing Seamless Switch

|
By int Status
Things used in this project × 1 As stated in the title, this time we aim to achieve seamless video processing transition based on our previously established design foundation. This post also requires reading the previous sections first to make implementation easier. Vivado The Block Design is primarily based on the previous one. Since the earlier Video Test Pattern Generator (TPG) was only used as a bypass, we can replace it with an AXI4-stream broadcaster.
Open in Who Shared Issue with article?

PYNQ-Z2 HDMI Usage - 3: Using Sobel Filter with HDMI

|
By int Status
This time, we will combine Build and Install OpenCV in Vitis HLS 2022.2 and PYNQ-Z2 HDMI Usage - 2: HDMI Passthrough to perform real-time Sobel filter image processing. Vitis HLS Based on Build and Install OpenCV in Vitis HLS 2022.2, we can directly execute Run Implementation. Then, the IP generated through Vitis HLS will be located in the solution1/impl/ip folder. Vivado Block Design We can first import the HLS IP generated earlier into Vivado.
Open in Who Shared Issue with article?

PYNQ-Z2 HDMI Usage - 2: HDMI Passthrough

|
By int Status
Things used in this project × 1 Introduction The previous article discussed using the PYNQ-Z2 TX to output the TPG’s colorbar function. In this article, we will use the PYNQ-Z2’s HDMI RX/TX to implement HDMI passthrough, and internally convert the signal into an AXI4-stream format for easier image processing in the future. Regarding the prerequisites—downloading the PYNQ-Z2 development board information, setting up the XDC, and configuring the IP—please refer to the previous article.
Open in Who Shared Issue with article?

PYNQ-Z2 HDMI Usage - 1: TPG Output

|
By int Status
Things used in this project × 1 Introduction I recently received a Pynq-Z2 development board. Since I’ve always been interested in image processing, this series will focus on image input, output, and processing. This post specifically demonstrates using the Pynq-Z2's HDMI output port to display TPG. Before starting to create a project, we need to import the PYNQ-Z2 board file into Vivado 2022.2 so that we can select the PYNQ-Z2 as the target board.
Open in Who Shared Issue with article?

Using CORDIC and DMA on the Ultra96 board

|
By int Status, RxBuffer Ptr
Things used in this project × 1 × 1 CORDIC (Coordinate Rotation Digital Computer) is a small and efficient algorithm to compute functions like spheric and hyperbolic trigonometry, square roots and more. Not as popular today as it was in the past but it still finds a place in the FPGA developer's toolbox. In this project I'm implementing the CORDIC IP block included in Vivado to perform calculation of sin and cos functions over an array of values.
Open in Who Shared Issue with article?

Tutorial: TFT SPI display on Xilinx Zynq SoC

|
By Viktor Nikolov, int Status
Things used in this project × 1 Hosyond 3.5 Inches TFT LCD Display Module 480x320 SPI ILI9488 × 1 This tutorial describes how to use a TFT SPI display on the AMD Xilinx Zynq-7000 SoC platform. Hardware We will use the 3.5″ ILI9488 TFT SPI 480x320 pixels display (which can be purchased on Amazon or on AliExpress; I'm not affiliated in any way). The reasons for selecting this particular display are simple: I like its size (it is not too small nor too big), and I prepared a SW library for it.
Open in Who Shared Issue with article?

ZYNQ使用AXI DMA(Scatter/Gather)模式进行PL与PS数据交互附源码（ps端移植freertos或者裸机）

|
By int Acsrmsg Index, int timeOut, int Status, Int BdCount
| CSDN
AXI DMA操作需要先提供一个在内存中驻留的不变空间，用于存储需要进行的DMA操作。形容这“每一次操作”的东西叫做Buffer Descriptor，缩写叫BD，这些BD是连接成链表的形式的，因为BD会动态增加，而预先分配存储BD的空间是恒定的，因此BD被连成一个环（BD Ring）,其实就是一个循环链表。 Scatter/Gather 允许一个数据包（Packet）由多个描述符（BD）来描述。官方文档指出的一个典型应用是在传输网络包时，Header和数据往往是分开存储的，利用SG模式可以较好的处理向多个目标读写的操作，提高应用吞吐量。 DB Ring中DB成链存放，为了解决环形结构带来的不知道Packet的起点和终点带来的问题，DMA使用了帧开始位 (TXSOF，TX Start of Frame bit) 和帧结束位 (TXEOF，TX End of Frame Bit)来分辨一段Packet。 当 DMA 获取设置了 TXSOF 位的描述符时，将触发Packet的开始。 Packet继续获取后续描述符，直到它获取一个设置了 TXEOF 位的描述符。 在接收 (S2MM)...
Open in Who Shared Issue with article?
Show More