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Articles by Jan Kaplon
MPA-SSA, design and test of a 65 nm ASIC-based system for particle tracking at HL-LHC featuring on-chip particle discrimination
Report number CMS-CR-2019-302 Title MPA-SSA, design and test of a 65 nm ASIC-based system for particle tracking at HL-LHC featuring on-chip particle discrimination Download Embed Viewed by 1 users Author(s) Ceresa, Davide (CERN) ; Bergamin, Gianmario (CERN) ; Caratelli, Alessandro (CERN) ; Jan Kaplon ; Kloukinas, Konstantinos (CERN) ; Scarfi', Simone (CERN) ; Yusuf Leblebici Imprint 11 Dec 2019. - 4 p.
Characterization of the MPA prototype, a 65 nm pixel readout ASIC with on-chip quick transverse momentum discrimination capabilities
Report number CMS-CR-2018-279 Title Characterization of the MPA prototype, a 65 nm pixel readout ASIC with on-chip quick transverse momentum discrimination capabilities Download Embed Viewed by 4 users Author(s) Ceresa, Davide (CERN) ; Caratelli, Alessandro (CERN) ; De Clercq, Jarne Theo (Vrije U., Brussels) ; Dena Giovinazzo ; Haranko, Mykyta (DESY) ; Jan Kaplon ; Kloukinas, Konstantinos (CERN) ; Jan Murdzek ; Scarfi', Simone (CERN) Imprint 15 Oct 2018. - 6 p.
Characterization of the first prototype of the Silicon-Strip readout ASIC (SSA) for the CMS Outer-Tracker phase-2 upgrade
CMS Note Report number CMS-CR-2018-286 Title Characterization of the first prototype of the Silicon-Strip readout ASIC (SSA) for the CMS Outer-Tracker phase-2 upgrade Author(s) Caratelli, Alessandro (CERN) ; Scarfi', Simone (CERN) ; Ceresa, Davide (CERN) ; De Clercq, Jarne Theo (Vrije U., Brussels) ; Haranko, Mykyta (DESY) ; Jan Kaplon ; Kloukinas, Konstantinos (CERN) ; Yusuf Leblebici Imprint 17 Oct 2018. - 6 p.
Readout architecture for the Pixel-Strip module of the CMS Outer Tracker Phase-2 upgrade
The Outer Tracker upgrade of the Compact Muon Solenoid (CMS) experiment at CERN introduces new challenges for the front-end readout electronics. In particular, the capability of identifying particles with high transverse momentum using modules with double sensor layers requires high speed real time interconnects between readout ASICs. The Pixel-Strip module combines a pixelated silicon layer with a silicon-strip layer.
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