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Articles by Yahya Can
[2406.16153] RowPress Vulnerability in Modern DRAM Chips
arXiv:2406.16153 (cs) View PDF HTML (experimental) Comments: Subjects: Hardware Architecture (cs.AR); Cryptography and Security (cs.CR) Cite as: arXiv:2406.16153 [cs.AR] (or arXiv:2406.16153v1 [cs.AR] for this version) Submission history From: Haocong Luo [ view email] [v1] Sun, 23 Jun 2024 16:26:35 UTC (1,155 KB) Bibliographic Tools Bibliographic Explorer Toggle Bibliographic Explorer () Litmaps Toggle Litmaps (What is Litmaps?) scite.ai Toggle scite Smart Citations (What are Smart...
Simultaneous Many-Row Activation in Off-the-Shelf DRAM Chips: Experimental Characterization and Analysis
[Submitted on 9 May 2024] Title:Simultaneous Many-Row Activation in Off-the-Shelf DRAM Chips: Experimental Characterization and Analysis Authors:Ismail Emir Yuksel , Yahya Can Tugrul , F. Nisa Bostanci , Geraldo F. Oliveira , A.
Spatial Variation-Aware Read Disturbance Defenses: Experimental Analysis of Real DRAM Chips and Implications on Future Solutions
[Submitted on 28 Feb 2024] Title:Spatial Variation-Aware Read Disturbance Defenses: Experimental Analysis of Real DRAM Chips and Implications on Future Solutions Download a PDF of the paper titled Spatial Variation-Aware Read Disturbance Defenses: Experimental Analysis of Real DRAM Chips and Implications on Future Solutions, by Abdullah Giray Ya\u{g}l{\i}k\c{c}{\i} and Yahya Can Tu\u{g}rul and Geraldo F.
PULSAR: Simultaneous Many-Row Activation for Reliable and High-Performance Computing in Off-the-Shelf DRAM Chips
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ABACuS: All-Bank Activation Counters for Scalable and Low Overhead RowHammer Mitigation
[Submitted on 15 Oct 2023 ( v1 ), last revised 23 Dec 2023 (this version, v2)] Title:ABACuS: All-Bank Activation Counters for Scalable and Low Overhead RowHammer Mitigation Download a PDF of the paper titled ABACuS: All-Bank Activation Counters for Scalable and Low Overhead RowHammer Mitigation, by Ataberk Olgun and Yahya Can Tugrul and Nisa Bostanci and Ismail Emir Yuksel and Haocong Luo and Steve Rhyner and Abdullah Giray Yaglikci and Geraldo F.
Ramulator 2.0: A Modern, Modular, and Extensible DRAM Simulator
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RowPress: Amplifying Read Disturbance in Modern DRAM Chips
arXivLabs is a framework that allows collaborators to develop and share new arXiv features directly on our website. Both individuals and organizations that work with arXivLabs have embraced and accepted our values of openness, community, excellence, and user data privacy. arXiv is committed to these values and only works with partners that adhere to them. Have an idea for a project that will add value for arXiv's community? Learn more about arXivLabs.
DRAM Bender: An Extensible and Versatile FPGA-based Infrastructure to Easily Test State-of-the-art DRAM Chips
arXivLabs is a framework that allows collaborators to develop and share new arXiv features directly on our website. Both individuals and organizations that work with arXivLabs have embraced and accepted our values of openness, community, excellence, and user data privacy. arXiv is committed to these values and only works with partners that adhere to them. Have an idea for a project that will add value for arXiv's community? Learn more about arXivLabs.
Sectored DRAM: A Practical Energy-Efficient and High-Performance Fine-Grained DRAM Architecture
[Submitted on 27 Jul 2022 ( v1 ), last revised 9 Jan 2024 (this version, v3)] Title:Sectored DRAM: A Practical Energy-Efficient and High-Performance Fine-Grained DRAM Architecture Download a PDF of the paper titled Sectored DRAM: A Practical Energy-Efficient and High-Performance Fine-Grained DRAM Architecture, by Ataberk Olgun and 8 other authors Download PDF HTML (experimental) Abstract:We propose Sectored DRAM, a new, low-overhead DRAM substrate that reduces wasted energy by enabling...
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