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Articles by Yusuf Leblebici
Low-power SEE hardening techniques and error rate evaluation in 65 nm readout ASICs
Report number CMS-CR-2019-190 Title Low-power SEE hardening techniques and error rate evaluation in 65 nm readout ASICs Author(s) Caratelli, Alessandro (CERN) ; Scarfi', Simone (CERN) ; Bergamin, Gianmario (CERN) ; Ceresa, Davide (CERN) ; De Clercq, Jarne Theo (Vrije U., Brussels) ; Kloukinas, Konstantinos (CERN) ; Yusuf Leblebici Imprint 08 Oct 2019. - 6 p.
MPA-SSA, design and test of a 65 nm ASIC-based system for particle tracking at HL-LHC featuring on-chip particle discrimination
Report number CMS-CR-2019-302 Title MPA-SSA, design and test of a 65 nm ASIC-based system for particle tracking at HL-LHC featuring on-chip particle discrimination Download Embed Viewed by 1 users Author(s) Ceresa, Davide (CERN) ; Bergamin, Gianmario (CERN) ; Caratelli, Alessandro (CERN) ; Jan Kaplon ; Kloukinas, Konstantinos (CERN) ; Scarfi', Simone (CERN) ; Yusuf Leblebici Imprint 11 Dec 2019. - 4 p.
Characterization of the first prototype of the Silicon-Strip readout ASIC (SSA) for the CMS Outer-Tracker phase-2 upgrade
CMS Note Report number CMS-CR-2018-286 Title Characterization of the first prototype of the Silicon-Strip readout ASIC (SSA) for the CMS Outer-Tracker phase-2 upgrade Author(s) Caratelli, Alessandro (CERN) ; Scarfi', Simone (CERN) ; Ceresa, Davide (CERN) ; De Clercq, Jarne Theo (Vrije U., Brussels) ; Haranko, Mykyta (DESY) ; Jan Kaplon ; Kloukinas, Konstantinos (CERN) ; Yusuf Leblebici Imprint 17 Oct 2018. - 6 p.
A System-Verilog Verification Environment for the CIC Data Concentrator ASIC of the CMS Outer Tracker Phase-2 Upgrades
The foreseen Phase-2 upgrades at the LHC present very challenging requirements for the front-end readout electronics of the CMS Outer Tracker detector. High data rates in combination with the employment of a novel technique for rejecting locally low transverse momentum particles as well as the strict low power consumption constraints require the implementation of an optimized readout architecture and specific interconnect synchronization schemes for its components.
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