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Articles by Alliances VP
Synopsys-AMD Webinar: Advancing 3DIC Design Through Next-Generation Solutions
Introduction of 2.5D and 3D multi-die based products are helping extend the boundaries of Moore’s Law, overcoming limitations in speed and capacity for high-end computational tasks. In spite of its critical function within the 3DIC paradigm, the interposer die’s role and related challenges are often neither fully comprehended nor appreciated.
Reduce Risk, Ensure Compliance: Hardware-Assisted Verification for Design Certification - Semiwiki
Prologue Peter was running late for two reasons. First, he encountered unexpected heavy traffic and arrived ten minutes late for a crucial meeting with a customer to run a compliance test of his new 6G phone design prototyped on FPGAs. This prototype’s success was pivotal, as it could secure a significant purchase order. Peter had reason to be confident.
What to Do with All that Data – AI-driven Analysis Can Help - Semiwiki
Today’s advanced node chip designs are faced with many new complexities from design and verification down to manufacturing. The solutions used at every stage of chip development generate petabytes of data. Managing, analyzing, understanding, and acting upon that data is overwhelming and paralyzing. Manual interpretation of that data is nearly impossible and at best leads to surface level analysis.
Follow the Leader – Synopsys Provides Broad Support for Processor Ecosystems - Semiwiki
Synopsys has expanded its ARC processor portfolio to include a family of RISC-V processors. This was originally reported on SemiWiki last October. There is also a recent in-depth article on the make-up of the ARC-V family on SemiWiki here. This is important and impactful news; I encourage you to read these articles if you haven’t done so already. What I want to cover in this post is a broader perspective on what Synopsys is doing to provide holistic support for the entire processor ecosystem.
Synopsys Accelerates Innovation on TSMC Advanced Processes
We all know that making advanced semiconductors is a team sport. TSMC can innovate the best processes, but without the right design flows, communication schemes and verified IP it becomes difficult to access those processes. Synopsys recently announced some details on this topic. It covers a lot of ground. The graphic at the top of this post will give you a feeling for the breadth of what was discussed.
ARC-V portfolio plus mature software IP targets three tiers
Synopsys is bridging its long-running ARC® processor IP strategy into a RISC-V architecture – Bernard Murphy introduced the news here on SemiWiki last November. We’re getting new insight from Synopsys on its ARC-V™ portfolio and how they see RISC-V IP plus their mature software development toolchain IP fitting customer needs in automotive, consumer, IoT, networking, storage, and other applications.
Synopsys is Paving the Way for Success with 112G SerDes and Beyond - Semiwiki
Data communication speeds continue to grow. New encoding schemes, such as PAM-4 are helping achieve faster throughput. Compared to the traditional NRZ scheme, PAM4 can send twice the signal by using four levels vs. the two used in NRZ. The diagram at the top of this post shows the how data density is increased. With progress comes challenges. PAM4 has a worse signal-to-noise ratio, and reflections are also much worse.
SoC Power Islands Verification with Hardware-assisted Verification
The ever-growing demand for longer battery life in mobile devices and energy savings in general have pushed power optimization to the top of designers’ concerns. While various techniques like multi-VT transistors and clock gating offer power savings at gate-level design, the real impact occurs at system level, where hardware and software collaborate. A key power savings feature in modern SoC designs is the ability to dynamically deactivate design sections temporarily not in use.
Lifecycle Management, FuSa, Reliability and More for Automotive Electronics
Synopsys recently hosted an information rich-webinar, modestly titled “Improving Quality, FuSa, Reliability, and Security in Automotive Semiconductors”. I think they undersold the event; this was really about managing all of those things through the lifecycle of a car, in line with auto OEMs strategies for the future of the car. The standout message for me was total lifecycle management, from initial semiconductor architecture and design through end-of-lifecycle.
Early SoC Dynamic Power Analysis Needs Hardware Emulation
The relentless pursuit for maximizing performance in semiconductor development is now matched by the crucial need to minimize energy consumption. Traditional simulation-based power analysis methods face insurmountable challenges to accurately capture complex designs activities in real-world scenarios. As the scale of modern SoC designs explodes, a new pre-silicon dynamic power analysis methodology is essential. This approach should center on executing representative real-world software workloads.
Synopsys Design IP for Modern SoCs and Multi-Die Systems
Semiconductor intellectual property (IP) plays a critical role in modern system-on-chip (SoC) designs. That’s not surprising given that modern SoCs are highly complex designs that leverage already proven building blocks such as processors, interfaces, foundational IP, on-chip bus fabrics, security IP, and others. This is reflected by a flourishing third-party IP market segment that reached $7.05B in 2023 [Source: IP Nest Reports].
Synopsys Presents AI-Fueled Innovation at SNUG 2024
SNUG is the premier event for Synopsys to showcase its technology and impact on the industry. This year’s SNUG did not disappoint. The two-day event packed many fantastic user presentations along with exciting news of innovation from Synopsys. Jensen Huang and Sassine Ghazi even held a live, interactive Q&A session. Compelling content. The tagline for the event was: Our Technology, Your Innovation, setting a tone of collaboration for the future.
Scaling Data Center Infrastructure for the Terabit Era
Earlier this month, SemiWiki wrote about Synopsys’s complete 1.6T Ethernet IP solution to drive AI and Hyperscale Data Center chips. A technology’s success is all about when, where and how it gets adopted within the ecosystem. In the high-speed ethernet ecosystem, the swift adoption of 1.6T Ethernet relies on key roles and coordinated actions.
TSMC and Synopsys Bring Breakthrough NVIDIA Computational Lithography Platform to Production
NVIDIA cuLitho Accelerates Semiconductor Manufacturing’s Most Compute-Intensive Workload by 40-60x, Opens Industry to New Generative AI Algorithms. An incredible example of semiconductor industry partnerships was revealed during the Synopsys User Group (SNUG) last month. It started with a press release but there is much more to learn here in regards to semiconductor industry dynamics. I saw a very energized Jensen Huang, co-founder and CEO of Nvidia, at GTC which was amazing.
Synopsys SNUG Silicon Valley Conference 2024: Powering Innovation in the Era of Pervasive Intelligence
After the leadership transition at the top, Synopsys had just a little more than two months before the company’s flagship event, the Synopsys User Group (SNUG) conference. The Synopsys user community and entire ecosystem were waiting to hear new CEO Sassine Ghazi’s keynote to learn where the company is going and its strategic vectors. Sassine, his executive team and the entire company delivered an amazing SNUG 2024.
2024 DVCon US Panel: Overcoming the challenges of multi-die systems verification - Semiwiki
2024 DVCon was very busy this year. Bernard Murphy and I were in attendance for SemiWiki, he has already written about it. Multi die and chiplets was again a popular topic. Lauro Rizzatti, a consultant specializing in hardware-assisted verification, moderated an engaging panel, sponsored by Synopsys, focusing on the intricacies of verifying multi-die systems.
Synopsys Enhances PPA with Backside Routing
Complexity and density conspire to make power delivery very difficult for advanced SoCs. Signal integrity, power integrity, reliability and heat can seem to present unsolvable problems when it comes to efficient power management. There is just not enough room to get it all done with the routing layers available on the top side of the chip. A strategy is emerging to deal with the problem that seems to take a page out of the multi-die playbook.
Complete 1.6T Ethernet IP Solution to Drive AI and Hyperscale Data Center Chips - Semiwiki
The demand for high-bandwidth, low-latency networking solutions has never been greater. As artificial intelligence (AI) workloads continue to grow exponentially, and hyperscale data centers become the backbone of our digital infrastructure, the need for faster and more efficient communication technologies becomes imperative. 1.6T Ethernet will rapidly be replacing 400G and 800G Ethernet as the backbone of hyperscale data centers.
2024 Signal & Power Integrity SIG Event Summary
It was a dark and stormy night here in Silicon Valley but we still had a full room of semiconductor professionals. I emceed the event. In addition to demos, customer and partner presentations, we did a Q&A which was really great. One thing I have to say is that Intel really showed up for both DesignCon and the Chiplet Summit. Quite a few Intel employees introduced themselves and a couple even took pictures with me, great networking.
Achieving Extreme Low Power with Synopsys Foundation IP Memory Compilers and Logic Libraries - Semiwiki
The relentless demand for lower power SoCs is evident across many markets. Examples include cutting-edge mobile, IoT, and wearable devices along with the high compute demands for AI and 5G/6G communications. Drivers for low power include battery life, thermal management and, for high compute applications, the overall cost of operation. Several approaches are available to achieve low power. A common thread for many is the need for optimal Foundation IP, that is, embedded memories and logic libraries.
Navigating the 1.6Tbps Era: Electro-Optical Interconnects and 224G Links - Semiwiki
In the relentless pursuit of ever-increasing data speeds, the 1.6 Terabits per second (Tbps) era looms on the horizon, promising unprecedented levels of connectivity and bandwidth within data centers. As data-intensive applications proliferate and the demand for real-time processing escalates, the need for robust and efficient communication infrastructure becomes paramount.
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