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1 INTRODUCTION HPC machines are typically optimized for throughput and not latency of individual jobs, where the batch queue system means that there is an unbounded time in which simulation jobs will wait in the queue.

1 INTRODUCTION Despite having made their debut on the HPC scene only a few years ago, Arm-based processors have already become some of the most powerful chips in the world. Advanced features of recent Arm architectures, such as the scalable vector extension (SVE), have enabled new optimizations that until very recently were not possible. One of these optimizations is the vectorization of loops containing modular arithmetic operations, in particular 64-bit modular multiplications.

On-chip infrastructure Figure 2 illustrates the architecture of the static part of the on-chip infrastructure in our approach. This is known as the shell, and is deployed to the FPGA to provide infrastructure and management capabilities such as configuration of the reconfigurable regions and the ability to share memory between the CPU and the reconfigurable logic. The blue box in Figure 2 represents the PL part of the Zynq FPGA, where each constituent box is known as an IP block.