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Geng-Chiau Liang on Muck Rack

Geng-Chiau Liang

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Low-power 2D CFETs using single-crystal high- κ dielectrics

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By Ji Zhang, Yu-Cheng Lu, Zeheng Wang, Yu-Ming Chang, Fangyuan Zheng, Zi-Liang Yang, Lingqi Li, Ang-Sheng Chou, Zongmeng Yang, Haomin Liu, Lin-Yun Huang, Chenyang Li, Chengdong Yao, Pengfei Yang, Wanying Li, Wanqing Meng, Ming-Yang Li, Chao-Ching Cheng, Dong-Keun Ki, Ya-Ping Chiu, Kah-Wee Ang, Yi Wan, Iuliana Radu, Sean E. Li, Jing-Kai Huang, Lain-Jong Li, Geng-Chiau Liang, Vita Pi-Ho Hu
| Nature Verified
Abstract Aggressive scaling in silicon electronics—although essential for improving power, performance, area and cost—faces increasing challenges in further reducing power consumption due to electrostatic and leakage constraints1,2. Achieving efficient operation at low supply voltages therefore requires new materials and gate-stack engineering strategies.
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