Ibrahem E. Atawi

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Abstract : The presence of the DC components in the grid voltage adversely affects the performance of the synchronization unit, causing oscillatory and offset errors in the estimated grid information. Several approaches were proposed to address the DC offset problem by incorporating an additional filtering stage to the synchronous reference frame phase-locked loop (SRF-PLL).

Abstract : This work proposes a structural enhancement and a new technique to design the loop filter (LF) of a third-order phase-locked loop (PLL) to enhance the PLL dynamic performance under abnormal grid conditions. The proposed PLL combines a moving average filter (MAF) and an arbitrarily delayed signal cancelation (ADSC) for structural enhancement to achieve DC-offset rejection and harmonics elimination.