Kauser Johar

Abstract Quantum error correction will be essential for quantum computers to realise their full potential. As quantum computers advance towards demonstrating a universal fault-tolerant logical gate set, implementing scalable and low-latency real-time decoding will be crucial to avoid an exponential slowdown and maintain a fast logical clock rate. Here, we demonstrate low-latency feedback with a scalable FPGA decoder integrated into the control system of a superconducting quantum processor.

By Kauser Johar, Chipletti Is SRAM Dead or Just Evolving? SRAM has powered CPU caches for decades, but its scaling has stalled—raising questions about its future. This talk explores SRAM’s origins, its rise in computing, and the limits of current scaling. We’ll introduce 3D chiplets as a path forward, highlight key break-even points in area, cost, and performance, and show how 3D SRAM can unlock next-generation AI inference, including trillion-parameter models.