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Ningyuan Yin

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Articles

Design of a High-Speed, Low-Power PTL-CMOS Hybrid Multiplier Using Critical-Path Evaluation Model

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By Yihe Yu, Wanyuan Pan, Chengcheng Tang, Ningyuan Yin
| MDPI
All articles published by MDPI are made immediately available worldwide under an open access license. No special permission is required to reuse all or part of the article published by MDPI, including figures and tables. For articles published under an open access Creative Common CC BY license, any part of the article may be reused without permission provided that the original article is clearly cited. For more information, please refer to https://www.mdpi.com/openaccess.
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Low-Power Pass-Transistor Logic-Based Full Adder and 8-Bit Multiplier

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By Chengcheng Tang, Ningyuan Yin, Wanyuan Pan, Yihe Yu
| MDPI
3.1. Circuit Design In this section, a novel PTL full adder is presented. The circuit of the proposed PTL full adder is shown in Figure 17. The novel proposed full adder consists of 18 transistors. Instead of using an inverter to produce XNOR from XOR, we used a parallel PTL XOR gate (“XOR2” conducting “ A ⊕ B ¯ ”) to provide XNOR. As a result, the inverter was no longer needed. Similar to 16T-1996 and 14T-1996, we used two pass gates to form a majority gate to produce the output carry “Co”.
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