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Articles by Roger Espasa
Vision-Language Models (VLM) – the next big thing in AI? - Semiwiki
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Semidynamics adds NoC partner and ONNX for RISC-V AI applications
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2025 Outlook with Volker Politz of Semidynamics
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Semidynamics: A Single-Software-Stack, Configurable and Customizable RISC-V Solution - Semiwiki
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Semidynamics: A Single-Software-Stack, Configurable and Customizable RISC-V Solution - Semiwiki
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Gazzillion Misses – Making the Memory Wall Irrelevant - Semiwiki
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Semidynamics Shakes Up Embedded World 2024 with All-In-One AI IP to Power Nextgen AI Chips - Semiwiki
Semidynamics takes a non-traditional approach to design enablement. Not long ago, the company’s Founder and CEO, Roger Espasa unveiled extreme customization at the RISC-V Summit. That announcement focused on a RISC-V Tensor Unit designed for ultra-fast AI solutions. Recently, at Embedded World 2024 the company took this strategy a step further with an All-In-One AI IP processing element.
RISC-V Summit Buzz – Semidynamics Founder and CEO Roger Espasa Introduces Extreme Customization - Semiwiki
Founded in 2016 and based in Barcelona, Spain, Semidynamics™ is the only provider of fully customizable RISC-V processor IP. The company delivers high bandwidth, high performance cores with vector units and tensor units targeted at machine learning and AI applications. There were some recent announcements from Semidynamics leading up to the RISC-V Summit that extend the company’s focus on customization.
RISC-V Summit Buzz – Semidynamics Founder and CEO Roger Espasa Introduces Extreme Customization - Semiwiki
Founded in 2016 and based in Barcelona, Spain, Semidynamics™ is the only provider of fully customizable RISC-V processor IP. The company delivers high bandwidth, high performance cores with vector units and tensor units targeted at machine learning and AI applications. There were some recent announcements from Semidynamics leading up to the RISC-V Summit that extend the company’s focus on customization.
Deeper RISC-V pipeline plows through vector-scalar loops
Many modern processor performance benchmarks rely on as many as three levels of cache staying continuously fed. Yet, new data-intensive applications like multithreaded generative AI and 4K image processing often break conventional caching, leaving the expensive execution units behind them stalled.
RISC-V 64 bit IP for High Performance
RISC-V as an Instruction Set Architecture (ISA) has grown quickly in commercial importance and relevance since its release to the open community in 2015, attracting many IP vendors that now provide a variety of RTL cores. Roger Espasa, CEO and Founder of Semidynamics, has presented at RISC-V events on how their IP is customized for compute challenges that require high bandwidth and high performance cores with vector units.
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