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Sresta Valasa on Muck Rack

Sresta Valasa

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Articles

Role of Si/dielectric interface traps on the reliability of tree-shaped complementary FETs for sub-3 nm technology nodes

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By B. Mounika, S. Shreyas Thanthri, Sresta Valasa, Venkata Ramakrishna Kotha, Narendar Vadthiya
| Nature Verified
Abstract Complementary (C) FETs enable superior scaling and electrostatics for sub-3 nm nodes but the increased Si/dielectric interface reliability a critical concern, and its impact on Tree-shaped CFETs is investigated for the first time in this work. The Si/dielectric interface trap density (Nit) is varied from 1 to 9 × 1012 cm− 2 for both acceptor and donor traps to evaluate their influence on digital, analog, RF, and circuit characteristics.
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