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Kuiming Ma

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Articles

Enhanced DSP Architecture for Small Floating-Point Based Deep Learning Accelerators on FPGAs

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By Chang Liu, Yuntao Zhang, Kuiming Ma
| Wiley Online Library Verified
K.Ma, C.Liu, Y.Zhang, Z.Chen, J.Xu, and B.Xiong, “Enhanced DSP Architecture for Small Floating-Point Based Deep Learning Accelerators on FPGAs,” International Journal of Circuit Theory and Applications (2026): 1–10, https://doi.org/10.1002/cta.70387. 1 Introduction The digital signal processing (DSP) hard blocks can efficiently implement specific arithmetic circuits in contrast with the implementation based on the look-up tables (LUTs) in the field-programmable gate array (FPGA).
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