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By Ping Yeung, Jin Hou, Vinayak Desai, and Jacob Wiltgen The complexity of automotive integrated circuits (ICs) has grown exponentially with the introduction of advanced driver-assistance systems and autonomous-drive technologies. Directly correlated to this hike in complexity is the increased burden of ensuring an IC is protected from random hardware faults—functional failures that occur unpredictably.
By Chris Kwok, Priya Viswanathan, and Ping Yeung Reset architectures are notoriously complex and difficult to verify. Today’s SoCs contain highly complex reset distributions and synchronization circuitry. Often, reset trees can be larger than clock trees and have many of the same potential issues. Verifying that a design can be correctly reset under all modes of operation presents significant challenges.
Here's a methodology for finding good "fishing spots" in the formal verification process. There's always that one angler who always catches a lot of fish, even when nobody else is having any “luck.” Largely that’s because those successful anglers know the best fishing holes. They know where the fish tend to hide and therefore where to cast their lines.
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