Sween Kang

The shift from monolithic to multi-die design is inevitable — but that's not to say it's straightforward. Traditional monolithic design has clear limitations. Diminishing yield and high cost-per-die become issues when a design nears reticle limits. At this point, multi-die integration can break the system into a series of smaller dies and to overcome scale and cost issues of scale.

When it comes to digital design implementation, each step in the RTL-to-GDSII process is highly compute intense. At the SoC level, you’re evaluating various floorplan options of hundreds of partitions to minimize latency in the interconnections and drive greater efficiencies. Once you’ve determined your floorplan, then it’s time to move on to the rest of the steps within every partition toward full-chip implementation and signoff.