Ashish Darbari

Article By : Nicky Khodadad, Nguyen Vu and Ashish Darbari Mixed-precision and transprecision computing expose hidden BF16 underflow issues, increasing floating-point verification complexity across AI hardware designs. Floating-point computations dominate the landscape of all AI/ML compute but also in automotive, avionics and healthcare.

By Ashish Darbari and Bing Xue It’d be inconceivable these days to design a modern high-performance SoC without a network-on-chip (NoC) fabric. AI hyperscalers are inherently multi-threaded and rely on using hundreds of processing elements (PEs). Crossbar-based fabric would just not scale. What also changes with the adoption of the NoC is how to handle coherency between PEs. ACE is no longer adequate, and the Arm CHI protocol is widely used to stitch the compute elements on a coherent NoC.

In the semiconductor industry, optimizing Power, Performance, and Area (PPA) is a key challenge for designers and architects. Balancing these three factors often involves making trade-offs. Improving one variable might lead to sacrificing others. For example, boosting performance may result in increased power consumption and a larger silicon area, or some power-reducing techniques might reduce performance.