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Articles by Mark Eslinger
Hopes Ladysmith does something about dilapidated properties, homeowners care
My wife and I moved to Ladysmith five years ago coming from the Stanley area, making us somewhat newcomers here. We shopped around for a while before buying a nice home and some property in Ladysmith. The Ladysmith area is beautiful with the rivers, lakes and outdoor activities to enjoy. We recently celebrated our family reunion in Memorial Park, and the family was impressed with how well kept and beautiful the park is, which leads us to why I feel it is necessary to write a comment.
The pitfalls of mixing formal and simulation: Examples of the trouble
Article By : Mark Eslinger, Joe Hupcey III, and Nicolae Tusinschi Three RTL DUT code examples illustrate the trouble that can occur when comparing the results from simulation and formal side-by-side. Driven by the need to objectively measure the progress of their verification efforts and the contributions of different verification techniques, IC designers have adopted coverage as a metric.
The pitfalls of mixing formal and simulation: Where trouble starts
By Mark Eslinger, Joe Hupcey and Nicolae Tusinschi (Siemens EDA) EDN (May 23, 2022) The most effective functional verification environments employ multiple analysis technologies, where the strengths of each are combined to reinforce each other to help ensure that the device under test (DUT) behaves as specified. However, this creates an inherent challenge of properly comparing—and combining—the results from each source to give a succinct, accurate picture of the verification effort’s true status.
Bug Hunt! Spiraling In On Formal Coverage Closure
By Mark Eslinger and Jin Hou Many companies have used formal verification to verify complex SoCs and safety-critical designs. Using formal verification to confirm design functionalities and to uncover functional bugs is emerging as an efficient verification approach. Although formal verification will not handle the complexity of a design at the SoC level, it is an efficient tool to verify the design blocks or IP comprehensively.
利用形式驗證找到更多‘Bug’ - 電子工程專輯
作者 Mark Eslinger, Ping Yeung 本文介紹在形式驗證過程中找到最佳「釣魚點」的方法。這種所謂的「河釣法」(river fishing)並不是從一種初始狀態開始形式驗證，而是在功能模擬軌跡中找到有價值的「釣魚點」，開始進行形式驗證… 經常有這樣的事情發生，有些人總可以釣到很多魚，而其他人卻沒有這樣好的「運氣」。在很大程度上，這是因為那些厲害的釣手們知道最佳的釣魚點。他們知道魚兒一般都藏在哪裡，於是就會在那裡放線。 同樣地，驗證的方法也可以引導我們找到合適的「釣魚點」，顯著增加我們捕獲‘bug’的數量。 本文提出一種利用功能模擬活動的方法，從模擬軌跡中找到有價值的「釣魚點」，進行形式驗證。我們稱這種方法為「河釣法」(river fishing)，但它並不是從一種初始狀態開始形式驗證，而是從功能模擬軌跡中挑選出一些可疑的點，然後從這些「釣魚點」開始形式驗證。 這種「河釣法」包含三個主要步驟： 從模擬軌跡中辨識並提取出一組合適的「釣魚點」。 根據形式驗證引擎執行狀況篩選並確定這些釣魚點的優先級。 在運算伺服器上啓動並監測多個形式驗證的執行。...
Catch More Bugs with Formal Verification
Here's a methodology for finding good "fishing spots" in the formal verification process. There's always that one angler who always catches a lot of fish, even when nobody else is having any “luck.” Largely that’s because those successful anglers know the best fishing holes. They know where the fish tend to hide and therefore where to cast their lines.
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