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Chun-Hsiang Chang on Muck Rack

Chun-Hsiang Chang

As seen in: Color Research & Application, Nature, MDPI, PNAS, Europa Press, The Lancet, EE Times, Semiconductor Engineering
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Articles

Reduce Memory Redesigns With Shift-Left

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By Chun-Hsiang Chang
| Semiconductor Engineering Verified
Engineering managers overseeing memory design know the pattern well: a promising architecture moves smoothly through schematic capture and into layout, only to stumble when integration testing reveals contention issues that force expensive redesigns. Address decoders that looked correct in isolation turn out to enable multiple banks simultaneously. Power switches configured for aggressive gating create rail conflicts under specific state combinations.
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Early Memory Contention Checks Reduce IC Design Risks

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By Chun-Hsiang Chang
| EE Times Verified
"Partner Content" allows today's industry thought leaders to share their unique insight and perspective with the greater ASPENCORE audience.
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Shift-Left Verification: Why Early Reliability Checks Matter

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By Chun-Hsiang Chang
| EE Times Verified
//php echo do_shortcode('[responsivevoice_button voice="US English Male" buttontext="Listen to Post"]') ?> Today’s AI-driven mobile and consumer electronics markets require IC designers to deliver more functionality in less space, all while meeting tight power and reliability constraints. As designs migrate below the 2 nm node and integrate numerous power domains, both technical and business risks multiply.
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