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Articles by Don Dingee
GaN foundries aligning efforts around system-level solutions
On the wide-bandgap semiconductor landscape, the outlook for gallium nitride (GaN) foundry services seemed set to crack and split following recent events. Concerns rose when major foundries departed, led by TSMC's announcement of its GaN exit; however, with ample warning, most customers quickly found alternatives. Wolfspeed also pulled back after a brief bankruptcy and rapid restructuring, refocusing its foundry business on pure-play silicon carbide (SiC).
8051: The Core That’s Still Probably in Your House or Car
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SRAM compilers targeting automotive SoCs on advanced nodes
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Configurable xSPI memory controller IP core is FuSa-ready
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WEBINAR: Intrinsic Techniques in RF Power Amplifier Design
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Securing UALink in AI clusters with UALinkSec-compliant IP
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WEBINAR: HBM4E Advances Bandwidth Performance for AI Training
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WEBINAR: Two-Part Series on RF Power Amplifier Design
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On the high-speed digital design frontier with Keysight’s Hee-Soo Lee
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eFPGA Archives
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IoT Archives
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EDA Archives
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WEBINAR: What It Really Takes to Build a Future-Proof AI Architecture? - Semiwiki
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Sophisticated soundscapes usher in cache-coherent multicore DSP
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Synopsys Archives
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CAST Archives
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WEBINAR: PCIe 7.0? Understanding Why Now Is the Time to Transition - Semiwiki
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Semidynamics Archives
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Webinar: RF board design flow examples for co-simulating active circuits
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Semidynamics adds NoC partner and ONNX for RISC-V AI applications
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TRNG for Automotive achieves ISO 26262 and ISO/SAE 21434 compliance
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Webinar: RF design success hinges on enhanced models and accurate simulation
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Mixel Archives
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Crosstalk, 2kAmp power delivery, PAM4, and LPDDR5 analysis at DesignCon
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Chiplet integration solutions from Keysight at Chiplet Summit
Key Takeaways Chiplet technologies are gaining momentum, particularly in AI and 5G/6G RFIC applications, with significant presentations made by Keysight at the Chiplet Summit. System-level electrical layer analysis is crucial for chiplet design, particularly to ensure signal integrity, which is impacted by interconnect standards like UCIe and BoW.
Chiplet integration solutions from Keysight at Chiplet Summit
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GaN HEMT modeling with ANN parameters targets extensibility
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Keysight EDA 2025 launches AI-enhanced design workflows
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MIPI solutions for driving dual-display foldable devices
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Linear pluggable optics target data center energy savings
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Spatial audio concepts targeted for earbuds and soundbars
Spatial audio technologies deliver more realistic sound by manipulating how the listener perceives sounds virtually sourced from different directions and distances in a 3D space. Where traditional surround sound technology uses various sound channels through many speakers positioned around a listener, spatial audio can deliver immersive experiences from fewer speakers in smaller packages, such as in a pair of earbuds or a compact soundbar.
First third-party ISO/SAE 21434-certified IP product for automotive cybersecurity
Increased processing and connectivity in automobiles are cranking up the priority for advanced cybersecurity steps to keep roads safe. Electronic vehicle interfaces, including 5G/6G, Bluetooth, Wi-Fi, GPS, USB, CAN, and others, offer convenience features for drivers and passengers, but open numerous attack vectors for hackers. Many vehicles now provide over-the-air (OTA) update capability for infotainment systems and mission-critical vehicle software, adding to security concerns.
PCIe design workflow debuts simulation-driven virtual compliance
PCIe design complexity continues rising as the standard for intrasystem communication evolves. An urgent need for more system bandwidth drives PCIe interconnects to multi-lane, multi-link, multi-level signaling. Classical PCIe design workflows leave designers with most of the responsibility for getting the requisite interconnect details right. These classical workflows also defer compliance testing until physical realization – when it can be too late to fix unforeseen chip problems.
Facing challenges of implementing Post-Quantum Cryptography
While researchers continue a march for more powerful quantum computers, cybersecurity measures are already progressing on an aggressive timeline to avoid potential threats. The urgency is partly in anticipation of a “store-now-decrypt-later” attack where compromised data, seemingly safe under earlier generations of encryption technology, is gathered and kept until quantum computers grow powerful enough to enable future decryption.
INTERVIEW: Bluespec RISC-V soft cores in Achronix FPGAs
Recently, a partnership between Achronix and Bluespec has been in the news. Bluespec RISC-V processors are available as soft cores in a Speedster®7t FPGA on Achronix’s VectorPath® PCIe development card or in a standalone Speedster7t FPGA. We spoke with executives from Achronix and Bluespec about the impetus for this effort and where it might lead.
ARC-V portfolio plus mature software IP targets three tiers
Synopsys is bridging its long-running ARC® processor IP strategy into a RISC-V architecture – Bernard Murphy introduced the news here on SemiWiki last November. We’re getting new insight from Synopsys on its ARC-V™ portfolio and how they see RISC-V IP plus their mature software development toolchain IP fitting customer needs in automotive, consumer, IoT, networking, storage, and other applications.
The latest ideas on time-sensitive networking for aerospace
Time-sensitive networking for aerospace and defense applications is receiving new attention as a new crop of standards and profiles approaches formal release, anticipated before the end of 2024. CAST, partnering with Fraunhofer IPMS, has developed a suite of configurable IP for time-sensitive networking (TSN) applications, with an endpoint IP core now running at 10Gbps and switched endpoint and multiport switch IP cores available at 1Gbps and extending to 10Gbps soon.
Self-heating and trapping enhancements in GaN HEMT models
High-fidelity models incorporating real-world, cross-domain effects are essential for accurate RF system simulation. The surging popularity of gallium nitride (GaN) technology in 5G base stations, satellite communication, defense systems, and other applications raises the bar for transistor modeling.
WEBINAR: The Rise of the DPU
The server and enterprise network boundary has seen complexity explode in recent years. What used to be a simple TCP/IP offload task for network interface cards (NICs) is transforming into full-blown network acceleration using a data processing unit (DPU), able to make decisions based on traffic routes, message content, and network context. Parallel data path acceleration on hundreds of millions of packets at speeds reaching 400 Gbps is where Achronix is putting its high-performance FPGAs to work.
Ultra-low-power MIPI use case for streaming sensors
MIPI built its reputation on the efficient streaming of data from camera sensors in mobile devices. It combines high-speed transfers with balanced power consumption, helping extend battery life while providing the responsiveness users expect. However, high speed is not the only mode of operation for a MIPI interface – specifications also enable low power modes for slower data transfers, going to an ultra-low-power shutdown state when data communication is inactive.
QuantumPro unifies superconducting qubit design workflow
To create quantum computing chips today, a typical designer must cobble various tools together, switching back and forth between them for different tasks. By contrast, EDA solutions such as Keysight Advanced Design System (ADS) unify a design workflow in a single interface with automated data exchange between features.
Chiplet ecosystems enable multi-vendor designs
Chiplets dominate semiconductor industry conversations right now – and after the recent Chiplet Summit, we expect the intensity to go up a couple of notches. One company name often heard is Blue Cheetah, and we had the opportunity to sit down with them recently to discuss their views and their just-announced design win at Tenstorrent.
Blue Cheetah Analog Design Archives
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WEBINAR: FPGA-Accelerated AI Speech Recognition
The three-step conversational AI (CAI) process – automatic speech recognition (ASR), natural language processing, and text-to-synthesized speech response – is now deeply embedded in the user experience for smartphones, smart speakers, and other devices. More powerful large language models (LLMs) can answer more queries accurately after appropriate training.
NoCs give architects flexibility in system-in RISC-V design
RISC-V tends to generate excitement over the possibilities for the processor core, any custom instruction extensions, and its attached memory subsystem. Those are all necessary steps to obtaining system-level performance. But is that attention sufficient? Architects who have ventured into larger system-on-chip (SoC) designs know how complicated interconnecting many IP blocks vying for data paths all at once can get.
Automotive-grade MIPI PHY IP drives multi-sensor solutions
Sensors are critical to every new automotive design, whether created for a driver or self-driving. Frame rates and resolution for car, truck, and SUV imaging systems continue to rise. Getting data from each sensor to a location in the vehicle with sufficient processing power may be challenging, especially when AI inference algorithms must work on data streams in real-time.
Pairing RISC-V cores with NoCs ties SoC protocols together
Designers have many paths for differentiating RISC-V solutions. One path launches into various RISC-V core customizations and extensions per the specification. Another focuses on selecting and assembling IP blocks in a complete system-on-chip (SoC) design around one or more RISC-V cores. A third is emerging: interconnecting RISC-V cores and other IP blocks with a network-on-chip (NoC) instead of a simple bus structure.
Keysight EDA 2024 delivers shift left for chiplet and PDK workflows
Much of the recent Keysight EDA 2024 announcement focuses on high-speed digital (HSD) and RF EDA features for Advanced Design System (ADS) and SystemVue users, including RF System Explorer, DPD Explorer (for digital pre-distortion), and design elements for 5G NTN, DVB-S2X, and satcom phased array applications. Two important new features in the Keysight EDA 2024 suite may prove crucial in EDA workflows for chiplets and PDKs (process design kits).
Deeper RISC-V pipeline plows through vector-scalar loops
Many modern processor performance benchmarks rely on as many as three levels of cache staying continuously fed. Yet, new data-intensive applications like multithreaded generative AI and 4K image processing often break conventional caching, leaving the expensive execution units behind them stalled.
Scaling LLMs with FPGA acceleration for generative AI
Large language model (LLM) processing dominates many AI discussions today. The broad, rapid adoption of any application often brings an urgent need for scalability. GPU devotees are discovering that where one GPU may execute an LLM well, interconnecting many GPUs often doesn’t scale as hoped since latency starts piling up with noticeable effects on user experience.
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